Late Design Changes (ECOs) for Sequentially Optimized High-Level Esterel Designs

Late changes in silicon design, called ECO, is a common although undesired practice. They happen due to last minute changes in the specifications or to design bugs found at the late stage, sometimes after the tapeout. At this stages going through the topdown design flow is infeasible, because it would take too long and lead to undesirably large perturbations to the physical layout. High-level design flows generally reduce the number of potential bugs. However, the need for ECO still exists since there is no guarantee that all bugs are eliminated and since the spec may change late in the game. Since high-level design often deploys more powerful optimization than manual design flows, it becomes harder to find the place in the final circuit where manual changes should be done in order to correct the behavior. It is also harder to trace circuit bugs and changes back to the high-level spec. A software analogy would be to of perform manual changes in a C executable compiled with -Ox options, while back-annotating these changes to the original C code. We will illustrate this general high-level design problem by an Esterel example, with heavy sequential circuit optimization performed by the Esterel compiler backend. The desired ECO flow is as follows. The original specification S is compiled by the Esterel compiler to a circuit netlist C0, which is further optimized to the final implementation C using combinational and sequential optimization methods. If late changes are required this circuit is transformed manually into another circuit netlist C∗ such that perturbations to C are minimal. To maintain the high-level specification consistent with the modified implementation and to verify the manual change to the implementation,